lithium niobate / 08 Industry / 8.3
8.3 Wafer size and lane rate
L1 Bigger wafers, faster lanes
Larger wafers carry more chips per process step; thin-film wafers (LNOI) are made by ion slicing and bonding. Between 2023 and 2026, 6- and 8-inch thin-film LN lines were announced in China, Europe, and Taiwan, two of them inside merchant silicon foundries (UMC/Wavetek T/C, X-FAB F). By 2026, vendors stated 200 Gb/s-per-lane TFLN products available and 400 Gb/s per lane sampling V.
Wafer outlines to scale, 1 unit = 1 mm12-inch dashed: LG
Product
| # | Date | Size | Milestone | Grade |
|---|---|---|---|---|
| 1 | 2020-08 | 4" and 6" | Wafer-scale TFLN PICs, 0.27 dB/cm, DUV lithography | reported |
| 2 | 2023-09 | 8" | Anpai 8-inch TFLN line completed (reporter claim) | T |
| 3 | 2024-03 | 8" | Jiufengshan Lab: first 8-inch Si-photonic TFLN wafer (reporter claim) | T |
| 4 | 2025 | 4" | 4-inch TFLN on quartz, > 110 GHz, VπL 2.92 V cm, 50% yield | reported |
| 5 | 2025-06 | 6" / 8" | Soitec 150 mm LNOI to CCRAFT; 200 mm shown | T |
| 6 | 2025-06-09 | 6" | CHIPX first 6-inch TFLN wafer | T |
| 7 | 2026-01-19 | 200 mm | Ligentec + X-FAB TFLN-on-SiN / SOI | F |
| 8 | 2026-03 | 200 mm | TFLN modulators on 200 mm Si in a BEOL CMOS foundry; 1.87 V cm best on wafer map; chip bandwidth 93-110 GHz (OFC 2026 W1A.3) | reported |
| 9 | 2026-03 | 6" / 8" | HyperLight + UMC / Wavetek volume production | T/C |
| 10 | 2026-06-03 | 8" bulk LN | TDG Holding states 8-inch LN in mass production | F |
| 11 | undated | 3"-8" | NanoLN lists LNOI and LTOI at 3, 4, 6, 8 inch | F |
| 12 | undated | 12" | 12-inch optical-grade LN wafer "prepared" (TDG, secondary, unsourced) | LG |
Milestone numbers match the table; marks dim with the product filter. Dies per wafer: next figure.
Product
milestones: 1
milestones: 3
milestones: 5
milestones: 8
milestones: 1, LG only
- 2020-084" and 6" · thin filmWafer-scale TFLN PICs, 0.27 dB/cm, DUV lithographyreported
- 2023-098" · thin filmAnpai 8-inch TFLN line completed (reporter claim)T
- 2024-038" · thin filmJiufengshan Lab: first 8-inch Si-photonic TFLN wafer (reporter claim)T
- 20254" · thin film4-inch TFLN on quartz, > 110 GHz, VπL 2.92 V cm, 50% yieldreported
- 2025-066" / 8" · thin filmSoitec 150 mm LNOI to CCRAFT; 200 mm shownT
- 2025-06-096" · thin filmCHIPX first 6-inch TFLN waferT
- 2026-01-19200 mm · thin filmLigentec + X-FAB TFLN-on-SiN / SOIF
- 2026-03200 mm · thin filmTFLN modulators on 200 mm Si in a BEOL CMOS foundry; 1.87 V cm best on wafer map; chip bandwidth 93-110 GHz (OFC 2026 W1A.3)reported
- 2026-036" / 8" · thin filmHyperLight + UMC / Wavetek volume productionT/C
- 2026-06-038" bulk LN · bulkTDG Holding states 8-inch LN in mass productionF
- undated3"-8" · thin filmNanoLN lists LNOI and LTOI at 3, 4, 6, 8 inchF
- undated12" · bulk12-inch optical-grade LN wafer "prepared" (TDG, secondary, unsourced)LG
Dies per wafer
A modulator die is long and narrow; the number that fits on a wafer grows faster than the wafer area because fewer dies are lost at the edge. Set the die size and the edge exclusion.
Dies per wafer: DPW = πd2/(4S) − πd/√(2S), d = D − 2Ederived
| wafer diameter D | 100 mm | 150 mm | 200 mm |
| formula DPW | 628 | 1,527 | 2,820 |
| whole dies placed (drawn) | 605 | 1,482 | 2,763 |
| ratio to 100 mm (placed) | 1.00 | 2.45 | 4.57 |
S = die area 10.00 mm2. Die size and edge exclusion: display parameters template; default 10 × 1 mm holds a 9 mm traveling-wave electrode (the li2026aa MZM of section 2.2 is 9 mm long). Gross count: no scribe lanes, flats, or yield. Wafers drawn to one scale.
100 mm; formula 628
150 mm; formula 1,527
200 mm; formula 2,820
DPW = πd2/(4S) − πd/√(2S) with d = D − 2 × edge exclusion and S = 10.00 mm2 derived; the drawn dies are the exact count of whole dies inside the dashed edge-exclusion circle. Die size and edge exclusion are display parameters template; the default 10 × 1 mm die holds a 9 mm electrode like the 2.2 MZM. No scribe lanes, flats, or yield. Wafers to one scale.
Lane rate: research and products
Research: symbol rate per device row, step = yearly maximum◆ TFLN ◇ TFLT
Bottom row: product milestones (grades F, V, T only). Hover a tag; the 400 G/lane tag lights research points above 200 GBd (PAM4, 2 bit per symbol). Maximum per year in the atlas sample; single demonstrations.
Diamonds: TFLN (filled) and TFLT (outline) device rows; steps: yearly maximum in the atlas sample; single demonstrations. Product milestones: grades F, V, T only. Hover a product tag; the 400 G/lane tag lights the research points above 200 GBd that make 400 Gb/s PAM4 possible (2 bit per symbol).
atlas eb97f96 · 2026-10-20 · fetched 2026-10-25 github.com/jwt625/eo-modulator-atlas, no license file upstream
L2 Milestones
Wafer milestones
| Date | Milestone | Wafer | Grade |
|---|---|---|---|
| 2020-08 | Wafer-scale TFLN PICs, 0.27 dB/cm, DUV lithography | 4" and 6" | reported |
| 2023-09 | Anpai 8-inch TFLN line completed (reporter claim) | 8" | T |
| 2024-03 | Jiufengshan Lab: first 8-inch Si-photonic TFLN wafer (reporter claim) | 8" | T |
| 2025 | 4-inch TFLN on quartz, > 110 GHz, VπL 2.92 V cm, 50% yield | 4" | reported |
| 2025-06 | Soitec 150 mm LNOI to CCRAFT; 200 mm shown | 6" / 8" | T |
| 2025-06-09 | CHIPX first 6-inch TFLN wafer | 6" | T |
| 2026-01-19 | Ligentec + X-FAB TFLN-on-SiN / SOI | 200 mm | F |
| 2026-03 | TFLN modulators on 200 mm Si in a BEOL CMOS foundry; 1.87 V cm best on wafer map; chip bandwidth 93-110 GHz (OFC 2026 W1A.3) | 200 mm | reported |
| 2026-03 | HyperLight + UMC / Wavetek volume production | 6" / 8" | T/C |
| 2026-06-03 | TDG Holding states 8-inch LN in mass production | 8" bulk LN | F |
| undated | NanoLN lists LNOI and LTOI at 3, 4, 6, 8 inch | 3"-8" | F |
| undated | 12-inch optical-grade LN wafer "prepared" (TDG, secondary, unsourced) | 12" | LG |
Lane-rate milestones
| Date | Milestone | Kind | Grade |
|---|---|---|---|
| 2018 | 100 GBd OOK, 112 Gb/s PAM4, hybrid Si-LN MZM (research; He et al. 2019) | research | reported |
| 2022 | 128 GBd PAM16, net 400 Gb/s IM/DD with a TFLN MZM (research) | research | reported |
| 2025-04-07 | AFR: TFLN 130 GBd CDM in volume shipment; 400 Gb/s/lane PAM4 TFLN chip debut | product | F/V |
| 2025 | 440 GBd single-wavelength PS-16-ASK through a TFLN modulator (research; outside the atlas sample) | research | reported |
| 2026-03 | 420 Gb/s/lane O-band PAM4 TOSA on TFLN, 210 GBd (OFC 2026 W4J.4) | research | reported |
| 2026-03 | 768 Gb/s line rate on a TFLT MZM (OFC 2026 Th4A.2, postdeadline) | research | reported |
| 2026-03-17 | HyperLight 1.6T-DR8 TFLN reference transceiver, 20 W | product | F/V |
| 2026-06 | HyperLight: 200 G/lane products available, 400 G/lane sampling | product | V |
Atlas yearly maximum symbol rate, TFLN: 2017 40, 2018 100, 2020 110, 2021 100, 2022 136, 2023 112, 2024 180, 2025 220, 2026 225 GBd; TFLT: 2024 208, 2025 208, 2026 226 GBd derived.
L3 Reading announcements
- A "line" announcement is not a capacity figure; wafer starts per month are public only as targets (CCRAFT 2,000 wafers per month by 2030 V).
- Bulk LN (SAW, 8-inch at TDG) and thin-film LN (LNOI, 8-inch foundry lines) are different wafer products; the ladder labels each milestone with its product.
- The 12-inch outline carries only an LG-graded secondary claim; no primary source for a 12-inch LN wafer was read.
- Die counts are gross: the formula πd2/(4S) − πd/√(2S) (usable diameter d, die area S) and the exact number of whole dies placed on a grid inside the usable circle (best of four offsets); no scribe lanes, flats, notch, or yield.