5.8 Cladding and annealing

L1 Phenomenon

After etching, the waveguides are usually covered with silicon dioxide, which protects them, lets electrodes sit closer, and changes how the crystal holds charge. Low deposition temperature and a final oxygen anneal both lower optical loss.

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19	PECVD SiO2 cladding	ridge

                                                
                                                
                                                
                                                
                                                
                                                
                                                
                                                
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19/23PECVD SiO2 cladding (ridge route)

L2 Model and data

Recipe	Value	Source; status
PECVD SiO₂	800 nm at 300 °C substrate temperature	P
ICPCVD SiO₂	800 nm at 80 °C, then re-anneal; mean Q_int 1.5 (PECVD), 2.5 (annealed), 5 million (annealed, ICPCVD, re-annealed)	P
PECVD, wafer-scale	800 nm after mask strip	P
PECVD	1.5 µm	P
PECVD	900 nm, before electrodes, with 1.8 µm electrode gap	P
Hydrogen-free PECVD (LiTaO₃ analog)	2 µm, avoids Si-OH overtone absorption near 1.5 µm; after 500 °C O₂ anneal	P
HSQ cladding	900 nm HSQ, EBL-defined, annealed 400 °C, 1 h; chosen over PECVD to suppress photorefraction	P
Uncladded rings	removing the dielectric cladding mitigates photorefraction in microrings	P(abs)

L3 Details and open points

Cladding also sets DC-drift behaviour (chapter 04); LN-metal interface control plus anneal slowed EO relaxation by more than 10⁴ P(abs). RC fits of about 11.9 ms with SiO₂ cladding vs about 88.6 µs uncladded are reported P(abs).
The anneal temperature must stay below what electrodes and bonding layers tolerate (BCB 320 °C Guarino et al. 2007; Nb superconducting electrodes cannot be annealed P).

← 5.7 Patterning 5.9 Electrodes →